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19-2152; Rev 2; 11/02
Differential LVPECL/LVECL/HSTL Receiver/Drivers
General Description
The MAX9321/MAX9321A are low-skew differential receiver/drivers designed for clock and data distribution. The differential input can be adapted to accept a single-ended input by connecting the on-chip VBB supply to an input as a reference voltage. The MAX9321/MAX9321A feature ultra-low propagation delay (172ps) and part-to-part skew (20ps) with 24mA maximum supply current, making these devices ideal for clock buffering or repeating. For interfacing to differential HSTL and LVPECL signals, these devices operate over a +2.25V to +3.8V supply range, allowing high-performance clock and data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, these devices operate from a -2.25V to -3.8V supply. Multiple pinouts are provided to simplify routing across a backplane to either side of a double-sided board. Both devices are offered in space-saving 8-pin SOT23, SO, and MAX packages.
Features
o Improved Second Source of the MC10LVEP16 (MAX9321) o +2.25V to +3.8V Differential HSTL/LVPECL Operation o -2.25V to -3.8V Differential LVECL Operation o Low 17mA Supply Current o 20ps Part-to-Part Skew o 172ps Propagation Delay o Minimum 300mV Output at 3GHz o Output Low for Open Input o ESD Protection >2kV (Human Body Model) o On-Chip Reference for Single-Ended Input o Available in Thermally Enhanced Exposed-Pad SO Package
MAX9321/MAX9321A
Ordering Information Applications
Precision Clock Buffers Low-Jitter Data Repeaters
PART MAX9321EKA-T MAX9321EUA* MAX9321ESA MAX9321AEUA* MAX9321AESA TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 8 SOT23-8 8 MAX 8 SO 8 SOT23-8 8 MAX 8 SO-EP** TOP MARK AALK -- -- AAIX -- --
MAX9321AEKA-T -40C to +85C
*Future product--contact factory for availability. **EP = Exposed pad.
Pin Configurations
VCC 1 VEE 2 D3 D4 VEE
MAX9321
VCC 60k 100k 100k
8Q 7Q 6 N.C. 5 VBB
N.C. 1 D2 100k D3
MAX9321
VCC 60k
8 VCC 7Q 6Q
100k VBB 4 5 VEE
SOT23 Pin Configurations continued at end of data sheet.
MAX/SO
________________________________________________________________ Maxim Integrated Products
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Differential LVPECL/LVECL/HSTL Receiver/Drivers MAX9321/MAX9321A
ABSOLUTE MAXIMUM RATINGS
VCC to VEE ..........................................................................+4.1V D or D .................................................. VEE - 0.3V to VCC + 0.3V D to D .................................................................................3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA VBB Sink/Source Current .................................................0.6mA Junction-to-Ambient Thermal Resistance in Still Air 8-Pin SOT23.............................................................+112C/W 8-Pin MAX ..............................................................+221C/W 8-Pin SO-EP ...............................................................+53C/W Junction-to-Ambient Thermal Resistance with 500 LFPM Airflow 8-Pin SOT23...............................................................+78C/W 8-Pin MAX ..............................................................+155C/W 8-Pin SO.....................................................................+99C/W Junction-to-Case Thermal Resistance 8-Pin SOT23...............................................................+80C/W 8-Pin MAX ................................................................+39C/W 8-Pin SO.....................................................................+40C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (D, D, Q, Q, VBB).............................>2kV Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = +2.25V to +3.8V, outputs loaded with 50 1% to VCC - 2.0V. Typical values are at VCC - VEE = +3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1-5)
PARAMETER SYMBOL CONDITIONS MIN DIFFERENTIAL INPUT (D, D) Single-Ended Input High Voltage VBB connected to D (VIL for VBB connected to D), Figure 1 VBB connected to D (VIH for VBB connected to D), Figure 1 VCC 1.210 VCC 1.145 VCC 1.085 -40C TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
VIH
VCC
VCC
VCC
V
Single-Ended Input Low Voltage High Voltage of Differential Input Low Voltage of Differential Input Differential Input Voltage Input High Current D Input Low Current D Input Low Current
VIL
VEE
VCC 1.65
VEE
VCC 1.545
VEE
VCC 1.485
V
VIHD VILD VIHD VILD IIH IILD IILD For VCC - VEE < 3.0V For VCC - VEE 3.0V
VEE + 1.2 VEE 0.1 0.1
VCC VCC 0.1 VCC VEE 3.0 150
VEE + 1.2 VEE 0.1 0.1
VCC VCC 0.1 VCC VEE 3.0 150
VEE + 1.2 VEE 0.1 0.1
VCC VCC 0.1 VCC VEE 3.0 150
V V
V
A A A
-10 -150
100 +150
-10 -150
100 +150
-10 -150
100 +150
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Differential LVPECL/LVECL/HSTL Receiver/Drivers
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = +2.25V to +3.8V, outputs loaded with 50 1% to VCC - 2.0V. Typical values are at VCC - VEE = +3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1-5)
PARAMETER SYMBOL CONDITIONS MIN DIFFERENTIAL OUTPUT (Q, Q) Single-Ended Output High Voltage Single-Ended Output Low Voltage Differential Output Voltage VOH Figure 1 VCC 1.135 VCC 0.885 VCC 1.07 VCC 0.82 VCC 1.01 VCC 0.76 V -40C TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
MAX9321/MAX9321A
VOL VOH VOL
Figure 1
VCC 1.935 550
VCC 1.685
VCC 1.87 550
VCC 1.62
VCC 1.81 550
VCC 1.56
V
Figure 1
mV
REFERENCE (VBB) Reference Voltage Output (Note 6) POWER SUPPLY Supply Current (Note 7) IEE 16 24 17 24 18 24 mA VBB IBB = 0.5mA VCC 1.55 VCC 1.31 VCC 1.445 VCC 1.245 VCC 1.385 VCC 1.185 V
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = +2.25V to +3.8V, outputs loaded with 50 1% to VCC - 2V, input frequency = 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to the smaller of 3V or VCC - VEE. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 8, 11)
PARAMETER Differential Input-toOutput Delay Part-to-Part Skew (Note 9) Added Random Jitter (Note 10) SYMBOL tPLHD, tPHLD tSKPP fIN = 1.5GHz, Clock pattern tRJ fIN = 3.0GHz, Clock pattern 0.6 1.5 0.6 1.5 0.6 1.5 CONDITIONS MIN Figure 2 145 -40C TYP 184 MAX 235 MIN 145 +25C TYP 172 MAX 245 MIN 130 +85C TYP 167 MAX 230 ps UNITS
25 1.7
90 2.8
20 1.7
100 2.8
20 1.7
100 2.8
ps
ps (RMS)
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Differential LVPECL/LVECL/HSTL Receiver/Drivers MAX9321/MAX9321A
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = +2.25V to +3.8V, outputs loaded with 50 1% to VCC - 2V, input frequency = 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to the smaller of 3V or VCC - VEE. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 8, 11)
PARAMETER Added Deterministic Jitter (Note 10) SYMBOL CONDITIONS MIN tDJ 3.0Gbps 223 -1 PRBS pattern VOH - VOL 300mV, Clock pattern, Figure 2 fMAX VOH - VOL 550mV, Clock pattern, Figure 2 2.0 2.0 2.0 -40C TYP 57 MAX 80 MIN +25C TYP 57 MAX 80 MIN +85C TYP 57 MAX 80 ps (p-p) UNITS
3.0
3.0
3.0 GHz
Switching Frequency
Output Rise/ Fall Time (20% to 80%)
tR , tF
Figure 2
50
88
120
50
89
120
50
90
120
ps
Note 1: Guaranteed by design and characterization. Note 2: Measurements are made with the device in thermal equilibrium. Note 3: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 4: DC parameters production tested at TA = +25C. Guaranteed by design and characterization over the full operating temperature range. Note 5: Single-ended input operation is limited to VCC - VEE 3.0V. Note 6: Use VBB as a reference for inputs on the same device only. Note 7: All pins open except VCC and VEE. Note 8: Guaranteed by design and characterization. Limits are set at 6 sigma. Note 9: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 10: Device jitter added to the input signal.
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Differential LVPECL/LVECL/HSTL Receiver/Drivers
Typical Operating Characteristics
(SO packages) (VCC = +3.3V, VEE = 0, input transition time = 125ps (20% to 80%), VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 1.5GHz, outputs loaded with 50 to VCC - 2V, TA = +25C, unless otherwise noted.)
MAX9321/MAX9321A
SUPPLY CURRENT, IEE vs. TEMPERATURE
MAX9321 toc01
OUTPUT AMPLITUDE, VOH - VOL vs. FREQUENCY
0.9 0.8 OUTPUT AMPLITUDE (V) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 87
MAX9321 toc02
TRANSITION TIME vs. TEMPERATURE
90 TRANSITION TIME (ps)
MAX9321 toc03
20 19 SUPPLY CURRENT (mA) 18 17 16 15 14 -40 -15 10 35 60
1.0
89
tF tR
88
0 85 0 500 1000 1500 2000 2500 3000 3500 FREQUENCY (MHz) -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
PROPAGATION DELAY vs. HIGH VOLTAGE OF DIFFERENTIAL INPUT, VIHD
MAX9321 toc04
PROPAGATION DELAY vs. TEMPERATURE
190 PROPAGATION DELAY (ps) 180 170 160 150 140 130 120 tPLHD
MAX9321 toc05
200 195 190 PROPAGATION DELAY (ps) 185 180 175 170 165 160 155 150 1.0 1.4 1.8 2.2 2.6 3.0 3.4 tPHLD tPLHD VIHD - VILD = 0.5V
200
tPHLD
3.8
-40
-15
10
35
60
85
VIHD (V)
TEMPERATURE (C)
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Differential LVPECL/LVECL/HSTL Receiver/Drivers MAX9321/MAX9321A
Pin Description (MAX9321)
PIN MAX/SO 1 2 3 4 5 6 7 8 SOT23 6 3 4 5 2 7 8 1 NAME N.C. D D VBB VEE Q Q VCC No Connection Noninverting Differential Input. 100k pulldown to VEE. Inverting Differential Input. 60k pullup to VCC and 100k pulldown to VEE. Reference Output Voltage. Connect to the inverting or noninverting input to provide a reference for single-ended operation. When used, bypass with a 0.01F ceramic capacitor to VCC; otherwise leave open. Negative Supply Voltage Inverting Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Output. Typically terminate with 50 resistor to VCC - 2V. Positive Supply Voltage. Bypass from VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. FUNCTION
Pin Description (MAX9321A)
PIN MAX/SO 1 2 3 4 5 6 7 8 SOT23 6 3 4 5 2 8 7 1 NAME N.C. D D VBB VEE Q Q VCC No Connection Inverting Differential Input. 60k pullup to VCC and 100k pulldown to VEE. Noninverting Differential Input. 100k pulldown to VEE. Reference Output Voltage. Connect to the inverting or noninverting input to provide a reference for single-ended operation. When used, bypass with a 0.01F ceramic capacitor to VCC; otherwise leave open. Negative Supply Voltage Noninverting Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Output. Typically terminate with 50 resistor to VCC - 2V. Positive Supply Voltage. Bypass from VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. FUNCTION
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Differential LVPECL/LVECL/HSTL Receiver/Drivers MAX9321/MAX9321A
D VIH D VIL VBB (CONNECTED TO D) VOH VOH - VOL Q VOL
Q
Figure 1. Switching with Single-Ended Input
D VIHD - VILD D tPLHD Q VOH - VOL Q tPHLD
VIHD VILD
VOH VOL
80% 0 (DIFFERENTIAL) (Q) - (Q) 20% tR
80% 0 (DIFFERENTIAL) 20% tF
Figure 2. Differential Transition Time and Propagation Delay Timing Diagram
Detailed Description
The MAX9321/MAX9321A are low-skew differential receiver/drivers designed for clock and data distribution. For interfacing to differential HSTL and LVPECL signals, these devices operate over a +2.25V to +3.8V supply range, allowing high-performance clock and data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, these devices operate from a -2.25V to -3.8V supply.
Inputs
The differential input can be configured to accept a single-ended input when operating at approximately VCC VEE = 3.0V to 3.8V. This is accomplished by connecting the on-chip reference voltage, VBB, to an input as a reference. For example, the differential D, D input is converted to a noninverting, single-ended input by connecting V BB to D and connecting the single-ended input to D. An inverting input is obtained by connecting
VBB to D and connecting the single-ended input to D. With the differential input configured as single ended (using VBB), the single-ended input can be driven to VCC and VEE or with a single-ended LVPECL/LVECL signal. When the differential input is configured as a singleended input (using VBB), the approximate supply range is VCC - VEE = 3.0V to 3.8V. This is because one of the inputs must be VEE + 1.2V or higher for proper operation of the input stage. VBB must be at least VEE + 1.2V because it becomes the high-level input when the other (single-ended) input swings below it. Therefore, minimum VBB = VEE + 1.2V. The minimum VBB output is VCC - 1.510V. Substituting the minimum VBB into VBB = VEE + 1.2V results in a minimum supply of 2.71V. Rounding up to a standard supply gives the single-ended operating supply range of VCC - VEE = 3.0V to 3.8V.
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Differential LVPECL/LVECL/HSTL Receiver/Drivers MAX9321/MAX9321A
When using the VBB reference output, bypass it with a 0.01F ceramic capacitor to VCC. If the VBB reference is not used, it can be left open. The VBB reference can source or sink 0.5mA. Use VBB only for an input on the same device as the VBB reference. The maximum magnitude of the differential input from D to D is 3.0V or VCC - VEE, whichever is less. This limit also applies to the difference between any reference voltage input and a single-ended input. The differential input has bias resistors that drive the output to a differential low when the inputs are open. The inverting input is biased with a 60k pullup to VCC and a 100k pulldown to VEE. The noninverting input is biased with a 100k pulldown to VEE. Specifications for the high and low voltage of the differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously (VILD cannot be higher than VIHD). capacitor closest to the device. Use multiple parallel vias for low inductance. When using the VBB reference output, bypass it with a 0.01F ceramic capacitor to VCC (if the VBB reference is not used, it can be left open).
Traces
Input and output trace characteristics affect the performance of the MAX9321/MAX9321A. Connect each signal of a differential input or output to a 50 characteristic impedance trace. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50 characteristic impedance through connectors and across cables. Reduce skew within a differential pair by matching the electrical length of the traces. The exposed-pad (EP) SO package can be soldered to the PC board for enhanced thermal performance. If the EP is not soldered to the PC board, the thermal resistance is the same as the regular SO package. The EP is connected to the chip VEE supply. Be sure that the pad does not touch signal lines or other supplies. Contact Maxim's Packaging department for guidelines on the use of EP packages.
Outputs
Output levels are referenced to VCC and are considered LVPECL or LVECL, depending on the level of the VCC supply. With VCC connected to a positive supply and VEE connected to GND, the output is LVPECL. The output is LVECL when VCC is connected to GND and VEE is connected to a negative supply. A single-ended input of at least VBB 100mV or a differential input of at least 100mV switches the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics table.
Output Termination
Terminate outputs through 50 to VCC - 2V or use an equivalent Thevenin termination. When a single-ended signal is taken from the differential output, terminate both outputs. For example, when Q is used as a singleended output, terminate both Q and Q.
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1F and 0.01F capacitors in parallel as close to the device as possible, with the 0.01F value TRANSISTOR COUNT: 162
Chip Information
Pin Configurations (continued)
VCC 1 VCC VEE 2 D3 D4 60k
MAX9321A
8Q 7Q 6 N.C.
N.C. 1 D2
VCC 60k
MAX9321A
8 VCC 7Q
100k 100k 100k 5 VBB VEE VBB 4 5 VEE D3 100k 6Q
SOT23
MAX/SO
8
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Differential LVPECL/LVECL/HSTL Receiver/Drivers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SOT23, 8L.EPS
MAX9321/MAX9321A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ______________________9 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
8L, SOIC EXP. PAD.EPS

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